The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with a bus line loading compensating circuit for improving transmission characteristics.
As semiconductor devices become more highly integrated, the size of the devices composing the chip become smaller. Nevertheless, as the chip size of semiconductor devices increases the length of transmission lines for the semiconductor device, e.g., input-output lines or data lines, become longer. Also, the number of circuits and devices connected to the transmission lines, e.g., bus lines, increases as well. Therefore, loading of the bus line driving circuits and devices also increases.
In addition, it is required that the semiconductor devices be operated at high speeds. Therefore, it is essential that there be a reduction in delay time on the bus lines for highly integrated and high-speed operated semiconductor devices. As a result, the reply characteristics and transmission characteristics of bus lines connecting the devices and circuits should be improved.
FIG. 1 is a circuit diagram showing a bus line connection according to the prior art.
As shown in FIG. 1, transmission signal IN is input to the input terminal of inverter 101 in input driver 100. Output terminal NA of inverter 101 is connected to one terminal of bus line 200, and the other terminal of bus line 200 is connected to input terminal NB of inverter 301 in receiver 300. Also, the output terminal of inverter 301 in receiver 300 transmits output signal OUT. The elements 201, 202, 203 and 204 are resistance components of the loading of the bus line 200, and the elements 205, 206, 207, 208 and 209 are capacitance components of the loading of the bus line 200.
That is, transmission signal IN is transmitted to inverter 101 in input input driver 100, and then the output signal from input input driver 100 is transmitted to inverter 301 in receiver 300 via the bus line. The bus line positioned between input input driver 100 and receiver 300 and the loading capacity thereof determines a transmission characteristic of transmission signal IN. The loading can be divided into resistance component R and capacitance component C which determine the transmission characteristics of speed and efficiency. As known by those skilled in the art, RC is a time constant.
Decreasing bus line loading for reducing the delay time of a transmission signal is advantageous in high speed operation. That is, a small RC constant is advantageous to high speed transmission, and thus many efforts to reduce the RC time constant have been undertaken. A method for reducing capacitive loading by adequately adjusting the space between bus lines, a method for increasing driver size, a method for minimizing the length of the bus lines by changing the chip architecture and so on are under study, but those methods have not yet been satisfactory.
That is, when the space between bus lines becomes too wide, chip size increases, which is disadvantageous in large-scale integration. When driver size becomes too large, that is, the area occupied by the driver becomes wide, chip efficiency deteriorates, power consumption increases, and serious noise due to peak current results. Moreover, because chip architecture substantially depends on the entire arrangement of logic circuits and bonding pads and core construction rather than bus line length, the method of changing the chip architecture for reducing the delay time of a bus line has limits.